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rev. pra information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the prop erty of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.8703 ? 2005 analog devices, inc. all rights reserved. dual 14-bit, 1.0 gsps d/a converter preliminary technical data ad9778 features ? 1.8/3.3 v single supply operation ? low power: 560 mw (i outfs = 20 ma; f dac = 1 gsps, 4 interpolation ? dnl = tbd lsb, inl = tbd lsb ? sfdr = tbd dbc to f out = 100 mhz ? aclr = 84 dbc @ 80 mhz if ? cmos data interface with autotracking input timing ? analog output: adjustable 10-30ma (rl=25 ? to 50 ? ) ? 100-lead exposed paddle tqfp package ? multiple chip synchronization interface ? 84db digital interpolation filter stopband attenuation ? digital inverse sinc filter applications ? wireless infrastructure direct conversion transmit diversity ? wideband communications systems: point-to-point wireless, lmds product description the ad9778 is a dual 14-bit high performance, high frequency dac that provides a sample rate of 1 gsps, permitting multi carrier generation up to its nyquist frequency. it includes features optimized for direct conversion transmit applications, including complex digital modulation and gain and offset compensation. the dac outputs are optimized to interface seamlessly with analog quadrature modulators such as the ad8349. a serial peripheral interface (spi) provides for programming many internal parameters and also enables read-back of status registers. the output current can be programmed over a range of 10ma to 30ma. the ad9778 is manufactured on an advanced 0.18 m cmos process and operates from 1.8v and 3.3v supplies for a total power consumption of 325mw. it is supplied in a 100-lead qfp package. product highlights ultra-low noise and intermodulation distortion (imd) enable high quality synthesis of wideband signals from baseband to high intermediate frequencies. single-ended cmos interface supports a maximum input rate of 300 msps with 1x interpolation. manufactured on a cmos process, the ad9778 uses a proprietary switching technique that enhances dynamic performance. the current outputs of the ad9778 can be easily configured for various single-ended or diffe rential circuit topologies. functional block diagram complex modulator clock generation/distribution 2x n*fdac/8 n = 1, 2, 3? 7 p2d[13:0] iout2_p iout2_n clk+ clk- dataclk_out 2x 2x 2x 2x 2x sinc -1 sinc -1 16-bit idac 16-bit qdac digital controller clock multiplier 2x/4x/8x gain gain offset offset reference & bias 10 10 10 10 power-on reset serial peripheral interface qlatch ilatch delay line delay line data assembler sdio sdo sclk csb iout1_p iout1_n vref rset aux1_p aux1_n aux2_p aux2_n p1d[13:0] sync_i sync_o figure 1 functional block diagram
ad9778 preliminary technical data rev. pra | page 2 of 34 table of contents specifications............................................................................................3 dc specifications ......................................................................3 digital specifications............................................................4 ac specifications.......................................................................4 pin function descriptions .....................................................................5 pin configuration....................................................................................6 interpolation filter coefficients............................................................7 interpolation filter response curves ................................8 characterization data ............................................................9 general description ..............................................................................12 serial peripheral interface................................................................12 general operation of the serial interface......................................12 instruction byte .................................................................................12 serial interface port pin descriptions ............................................12 msb/lsb transfers ...........................................................................13 notes on serial port operation .......................................................13 spi register map ...............................................................................14 internal reference/full sc ale current ge neration .......................22 auxiliary dacs..................................................................................22 power down and sleep modes ........................................................22 internal pll clock multiplier / clock distribution.....................23 timing information ..........................................................................23 interpolation filter architecture.....................................................25 evaluation board schematics..............................................................27 revision history revision pra: initial version
preliminary technical data ad9778 rev. pra | page 3 of 34 specifications 1 dc specifications (vdd33 = 3.3 v, vdd18 = 1.8 v, maximum sample rate, unless otherwise noted) parameter temp test level min typ max unit resolution 14 bits integral nonlinearity (dnl) tbd lsb accuracy differential nonlinearity (inl) tbd lsb offset error tbd % fsr gain error (with internal reference) tbd % fsr gain error (without internal reference) tbd % fsr full scale output current 10 20 30 ma output compliance range 1.0 v output resistance tbd k ? analog outputs output capacitance tbd pf offset tbd ppm/ c gain tbd ppm/ c temperature drift reference voltage tbd ppm/ c internal reference voltage 1.2 v reference output current 100 na vdda33 3.13 3.3 3.47 v analog supply voltages vdda18 1.70 1.8 1.90 v vddd33 3.13 3.3 3.47 v vddd18 1.70 1.8 1.90 v digital supply voltages vddclk 1.70 1.8 1.90 v 600 msps tbd mw power consumption standby power tbd mw table 1: dc specifications 1 specifications subject to change without notice
ad9778 preliminary technical data rev. pra | page 4 of 34 digital specifications (vdd33 = 3.3 v, vdd18 = 1.8 v, maximum sample rate, unless otherwise noted) parameter temp test level min typ max unit differential peak-to-peak voltage 800 mv common mode voltage 400 mv dac clock input (clk+, clk-) maximum clock rate 1 gsps maximum clock rate (sclk) 40 mhz maximum pulse width high tbd ns serial peripheral interface maximum pulse width low tbd ns table 2: digital specifications ac specifications (vdd33 = 3.3 v, vdd18 = 1.8 v, maximum sample rate, unless otherwise noted) parameter temp test level min typ max unit output settling time (tst) (to 0.025%) tbd ns output rise time (10% to 90%) tbd ns output fall time (90% to 10%) tbd ns dynamic performance output noise (ioutfs=20ma) tbd pa/rthz f dac = 100 msps, f out = 20 mhz 79 dbc f dac = 200 msps, f out = 50 mhz 79 dbc f dac = 400 msps, f out = 70 mhz 81 dbc spurious free dynamic range (sfdr) f dac = 800 msps, f out = 70 mhz 84 dbc f dac = 200 msps, f out = 50 mhz 88 dbc f dac = 400 msps, f out = 60 mhz 85 dbc f dac = 400 msps, f out = 80 mhz 78 dbc two-tone intermodulation distortion (imd) f dac = 800 msps, f out = 100 mhz 85 dbc f dac = 156 msps, f out = 60 mhz -155 dbm/hz f dac = 200 msps, f out = 80 mhz -154 dbm/hz f dac = 312 msps, f out = 100 mhz -156 dbm/hz noise spectral density (nsd) f dac = 400 msps, f out = 100 mhz -156 dbm/hz f dac = 245.76 msps, f out = 20 mhz 77 dbc f dac = 491.52 msps, f out = 100 mhz 76 dbc wcdma adjacent channel leakage ratio (aclr), single carrier f dac = 491.52 msps, f out = 200 mhz 71 dbc f dac = 245.76 msps, f out = 60 mhz 75 dbc f dac = 491.52 msps, f out = 100 mhz 77 dbc wcdma second adjacent channel leakage ratio (aclr), single carrier f dac = 491.52 msps, f out = 200 mhz 73 dbc table 3: ac specifications
preliminary technical data ad9778 rev. pra | page 5 of 34 pin function descriptions pin no. name description pin no. name description 1 vddc18 1.8 v clock supply 51 p2d<6> port 2 data input d6 2 vddc18 1.8 v clock supply 52 p2d<5> port 2 data input d5 3 vssc clock common 53 vddd18 1.8 v digital supply 4 vssc clock common 54 vssd digital common 5 clk+ differential clock input 55 p1d<4> port 2 data input d4 6 clk- differential clock input 56 p1d<3> port 2 data input d3 7 vssc clock common 57 p1d<2> port 2 data input d2 8 vssc clock common 58 p1d<1> port 2 data input d1 9 vddc18 1.8 v clock supply 59 p1d<0> port 2 data input d0 (lsb) 10 vddc18 1.8 v clock supply 60 vddd18 1.8 v digital supply 11 vssc clock common 61 vddd33 3.3 v digital supply 12 vssc clock common 62 sync_o- diffe rential synchronization output 13 sync_i+ differential synchronization input 63 sync_o+ differential synchronization output 14 sync_i- differential synchronizat ion input 64 vssd digital common 15 vssd digital common 65 pll_lock pll lock indicator 16 vddd33 3.3 v digital supply 66 spi_sdo spi port data output 17 p1d<15> port 1 data input d15 (msb) 67 spi_sdio spi port data input/output 18 p1d<14> port 1 data input d14 68 spi_clk spi port clock 19 p1d<13> port 1 data input d13 69 spi_csb spi port chip select bar 20 p1d<12> port 1 data input d12 70 reset reset 21 p1d<11> port 1 data input d11 71 irq interrupt request 22 vssd digital common 72 vss analog common 23 vddd18 1.8 v digital supply 73 iptat reference current 24 p1d<10> port 1 data input d10 74 vref voltage reference output 25 p1d<9> port 1 data input d9 75 i120 120 a reference current 26 p1d<8> port 1 data input d8 76 vdda33 3.3 v analog supply 27 p1d<7> port 1 data input d7 77 vssa analog common 28 p1d<6> port 1 data input d6 78 vdda33 3.3 v analog supply 29 p1d<5> port 1 data input d5 79 vssa analog common 30 p1d<4> port 1 data input d4 80 vdda33 3.3 v analog supply 31 p1d<3> port 1 data input d3 81 vssa analog common 32 vssd digital common 82 vssa analog common 33 vddd18 1.8 v digital supply 83 iout2_p differential dac current output, channel 2 34 p1d<2> port 1 data input d2 84 iout2_n differential dac current output, channel 2 35 p1d<1> port 1 data input d1 85 vssa analog common 36 p1d<0> port 1 data input d0 (lsb) 86 aux2 _p auxiliary dac voltage output, channel 2 37 dataclk_out data clock output 87 aux2_n auxiliary dac voltage output, channel 2 38 vddd33 3.3 v digital supply 88 vssa analog common 39 txenable transmit enable 89 aux1_n auxiliary dac voltage output, channel 1 40 p2d<15> port 2 data input d15 (msb) 90 aux1 _p auxiliary dac voltage output, channel 1 41 p2d<14> port 2 data input d14 91 vssa analog common 42 p2d<13> port 2 data input d13 92 iout1_n differential dac current output, channel 1 43 vddd18 1.8 v digital supply 93 iout1_p differential dac current output, channel 1 44 vssd digital common 94 vssa analog common 45 p2d<12> port 2 data input d12 95 vssa analog common 46 p2d<11> port 2 data input d11 96 vdda33 3.3 v analog supply 47 p2d<10> port 2 data input d10 97 vssa analog common 48 p2d<9> port 2 data input d9 98 vdda33 3.3 v analog supply 49 p2d<8> port 2 data input d8 99 vssa analog common 50 p2d<7> port 2 data input d7 100 vdda33 3.3 v analog supply table 4: pin function descriptions
ad9778 preliminary technical data rev. pra | page 6 of 34 pin configuration vddd1 8 vddd1 8 vssd p2d<3> p2d<2> p2d<1> p2d<0> nc nc sync_ o- spi_sdo spi_sdi 51 52 53 54 vdda33 vssa vdda33 vssa vdda33 vssa aux2_p aux2_n vssa iout2_p iout2_n vssa vssa vssa iout1_n iout1_p vssa aux1_n 76 77 78 79 vssd vddd3 3 vssd vddd1 8 p1d<8> p1d<9> p1d<10> p1d<11> p1d<12> p1d<13> sync_ i- sync_ i+ vssc vssc p2d<9 > vddd33 p2d<10> p2d<11> p2d<12> p2d<13> dclk nc p1d<0> p1d<1> vddd18 vssd p1d<2> p1d<3> p1d<4> p1d<5> p1d<6> p1d<7> 27 26 p2d<5> p2d<6> p2d<7> p2d<8 > 50 49 aux1_p vssa vdda33 vssa vdda33 clk- clk+ vddc1 8 vssc vssc 3 2 vddc1 8 vssc vssc vddc1 8 1 vddc1 8 25 24 75 74 100 99 spi_clk spi_csb reset iptat vref irq ad9778 vssa vdda33 sync_ o+ vssd vss txenable p2d<4> 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 6 5 4 9 8 7 12 11 10 15 14 13 18 17 16 21 20 19 23 22 34 33 30 29 28 32 31 36 35 43 42 39 38 37 41 40 48 47 44 46 45 80 81 84 82 83 85 86 89 87 88 90 91 94 92 93 95 98 96 97 i120 pll_lock analog domain digital domain vddd18 vssd vddd3 3 nc figure 2. pin configuration
preliminary technical data ad9778 rev. pra | page 7 of 34 interpolation filter coefficients table 5: halfband filter 1 lower coefficient upper coefficient integer va lu e h(1) h(55) -4 h(2) h(54) 0 h(3) h(53) 13 h(4) h(52) 0 h(5) h(51) -34 h(6) h(50) 0 h(7) h(49) 72 h(8) h(48) 0 h(9) h(47) -138 h(10) h(46) 0 h(11) h(45) 245 h(12) h(44) 0 h(13) h(43) -408 h(14) h(42) 0 h(15) h(41) 650 h(16) h(40) 0 h(17) h(39) -1003 h(18) h(38) 0 h(19) h(37) 1521 h(20) h(36) 0 h(21) h(35) -2315 h(22) h(34) 0 h(23) h(33) 3671 h(24) h(32) 0 h(25) h(31) -6642 h(26) h(30) 0 h(27) h(29) 20755 h(28) 32768 table 6: halfband filter 2 lower coefficient upper coefficient integer va lu e h(1) h(23) -2 h(2) h(22) 0 h(3) h(21) 17 h(4) h(20) 0 h(5) h(19) -75 h(6) h(18) 0 h(7) h(17) 238 h(8) h(16) 0 h(9) h(15) -660 h(10) h(14) 0 h(11) h(13) 2530 h(12) 4096 table 7: halfband filter 3 lower coefficient upper coefficient integer va lu e h(1) h(15) -39 h(2) h(14) 0 h(3) h(13) 273 h(4) h(12) 0 h(5) h(11) -1102 h(6) h(10) 0 h(7) h(9) 4964 h(8) 8192 table 8: inverse sinc filter lower coefficient upper coefficient integer va lu e h(1) h(9) 2 h(2) h(8) -4 h(3) h(7) 10 h(4) h(6) -35 h(5) 401
ad9778 preliminary technical data rev. pra | page 8 of 34 interpolation filter response curves -4 -3 -2 -1 0 1 2 3 4 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 figure 3. ad9778 2x interpolation, low pass response to 4x input data rate (dotted lines indicate 1dbroll-off) -4 -3 -2 -1 0 1 2 3 4 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 figure 4. ad9778 4x interpolation, low pass response to 4x input data rate (dotted lines indicate 1dbroll-off) -4 -3 -2 -1 0 1 2 3 4 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 figure 5.ad9778 8x interpolation, low pass response to 4x input data rate (dotted lines indicate 1dbroll-off)
preliminary technical data ad9778 rev. pra | page 9 of 34 characterization data tbd figure 6. ad9778 typical inl tbd figure 7. ad9778 typical dnl tbd figure 8. sfdr vs. f out , 1x interpolation tbd figure 9. sfdr vs. f out , 2x interpolation tbd figure 10. sfdr vs. f out , 4x interpolation tbd figure 11. sfdr vs. f out , 8x interpolation
ad9778 preliminary technical data rev. pra | page 10 of 34 tbd figure 12. third order imd vs. f out , 1x interpolation tbd figure 13. third order imd vs. f out , 2x interpolation tbd figure 14. third order imd vs. f out , 4x interpolation tbd figure 15. third order imd vs. f out , 8x interpolation tbd figure 16. noise spectral density vs. f out , 1x interpolation tbd figure 17. noise spectral density vs. f out , 2x interpolation
preliminary technical data ad9778 rev. pra | page 11 of 34 tbd figure 18. aclr for 1 st adjacent band wcdma, 4x interpolation. on-chip modulation is used to translate baseband signal to if. tbd figure 19. aclr for 2nd adjacent band wcdma, 4x interpolation. on-chip modulation is used to translate baseband signal to if. tbd figure 20. aclr for 3rd adjacent band wcdma, 4x interpolation. on-chip modulation is used to translate baseband signal to if. 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0 25 50 75 100 125 150 175 200 225 250 f data (msps) power - w 8x interpolation, zero stuffing 4x interpolation, zero stuffing 4x interpolation 2x interpolation, zero stuffing 2x interpolation 1x interpolation, zero stuffing 1x interpolation 8x interpolation figure 21. power dissipation, single dac mode 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 0 25 50 75 100 125 150 175 200 225 250 f data (msps) power - w 8x interpolation, zero stuffing 8x interpolation,f da c /4 modulation 4x interpolation, zero stuffing 8x interpolation,f da c /2 modulation 8x interpolation,f da c /8 modulation 8x interpolation,modulation off 4x interpolation,f da c /4 modulation 4x interpolation,f da c /2 modulation 4x interpolation,modulation off 2x interpolation, zero stuffing 2x interpolation,f da c /2 modulation 2x interpolation,modulation off 1x interpolation, zero stuffing 1x interpolation figure 22. power dissipation, dual dac mode 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0 200 400 600 800 1000 1200 f dac - msps power - w figure 23. power dissipation of inverse sinc filter
ad9778 preliminary technical data rev. pra | page 12 of 34 general description the ad9778 combines many features which make it make it a very attractive dac for wired and wireless communications systems. the dual digital signal path and dual dac structure allow an easy interface with common quadrature modulators when designing single sideband transmitters. the speed and performance of the ad9778 allow wider bandwidths/more carriers to be synthesized than with previously available dacs. the digital engine in the ad9778 uses a breakthrough filter architecture that combines the interpolation with a digital quadrature modulator. this allows the ad9778 to do digital quadrature frequency up conversion. the ad9778 also has features which allow simplified synchronization with incoming data, and also allows multiple ad9778s to be synchronized. serial peripheral interface ad9778 spi port spi_csb (pin 69) spi_sclk (pin 68) spi_sdi (pin 67) spi_sdo (pin 66) figure 24. ad9778 spi port the ad9778 serial port is a flexible, synchronous serial communications port allowing easy interface to many industry- standard microcontrollers and microprocessors. the serial i/o is compatible with most synchronous transfer formats, including both the motorola spi? and intel? ssr protocols. the interface allows read/write access to all registers that configure the ad9778. single or multiple byte transfers are supported, as well as msb first or lsb first transfer formats. the ad9778s serial interface port can be configured as a single pin i/o (sdio) or two unidirectional pins for in/out (sdio/sdo). general operation of the serial interface there are two phases to a communication cycle with the ad9778. phase 1 is the instruction cycle, which is the writing of an instruction byte into the ad9778, coincident with the first eight sclk rising edges. the instruction byte provides the ad9778 serial port controller with information regarding the data transfer cycle, which is phase 2 of the communication cycle. the phase 1 instruction byte defines whether the upcoming data transfer is read or write, the number of bytes in the data transfer, and the starting register address for the first byte of the data transfer. the first eight sclk rising edges of each communication cycle are used to write the instruction byte into the ad9778. a logic high on the cs pin, followed by a logic low, will reset the spi port timing to the initial state of the instruction cycle. this is true regardless of the present state of the internal registers or the other signal levels present at the inputs to the spi port. if the spi port is in the midst of an instruction cycle or a data transfer cycle,none of the present data will be written. the remaining sclk edges are for phase 2 of the communication cycle. phase 2 is the actual data transfer between the ad9778 and the system controller. phase 2 of the communication cycle is a transfer of 1, 2, 3, or 4 data bytes as determined by the instruction byte. using one multibyte transfer is the preferred method. single byte data transfers are useful to reduce cpu overhead when register access requires one byte only. registers change immediately upon writing to the last bit of each transfer byte. instruction byte the instruction byte contains the information shown in error! reference source not found. . msb lsb i7 i6 i5 i4 i3 i2 i1 i0 r/w n1 n0 a4 a3 a2 a1 a0 table 9. spi instruction byte r/w , bit 7 of the instruction byte, determines whether a read or a write data transfer will occur after the instruction byte write. logic high indicates read operation. logic 0 indicates a write operation. n1, n0 , bits 6 and 5 of the instruction byte, determine the number of bytes to be transferred during the data transfer cycle. the bit decodes are shown in table 10. a4, a3, a2, a1, a0 , bits 4, 3, 2, 1, 0 of the instruction byte, determine which register is accessed during the data transfer portion of the communications cycle. for multibyte transfers, this address is the starting byte address. the remaining register addresses are generated by the ad9778 based on the lsbfirst bit (reg00, bit 6). n1 n2 description 0 0 transfer 1 byte 0 1 transfer 2 bytes 1 0 transfer 3 bytes 1 1 transfer 4 bytes table 10. byte transfer count serial interface port pin descriptions sclkserial clock . the serial clock pin is used to synchronize data to and from the ad9778 and to run the internal state machines. sclks maximum frequency is 20 mhz. all data input to the ad9778 is registered on the rising edge of sclk. all data is driven out of the ad9778 on the falling edge of sclk. csbchip select . active low input starts and gates a communication cycle. it allows more than one device to be used on the same serial communications lines. the sdo and sdio pins will go to a high impedance state when this input is high. chip select should stay low during the entire communication cycle.
preliminary technical data ad9778 rev. pra | page 13 of 34 sdioserial data i/o . data is always written into the ad9778 on this pin. however, this pin can be used as a bidirectional data line. the configuration of this pin is controlled by bit 7 of register address 00h. the default is logic 0, which configures the sdio pin as unidirectional. sdoserial data out . data is read from this pin for protocols that use separate lines for transmitting and receiving data. in the case where the ad9778 operates in a single bidirectional i/o mode, this pin does not output data and is set to a high impedance stat e. msb/lsb transfers the ad9778 serial port can support both most significant bit (msb) first or least significant bit (lsb) first data formats. this functionality is controlled by register bit lsbfirst (reg00, bit 6). the default is msb first (lsbfirst = 0). when lsbfirst = 0 (msb first) the instruction and data bytes must be written from most significant bit to least significant bit. multibyte data transfers in msb first format start with an instruction byte that includes the register address of the most significant data byte. subsequent data bytes should follow in order from high address to low address. in msb first mode, the serial port internal byte address generator decrements for each data byte of the multibyte communication cycle. when lsbfirst = 1 (lsb first) the instruction and data bytes must be written from least significant bit to most significant bit. multibyte data transfers in lsb first format start with an instruction byte that includes the register address of the least significant data byte followed by multiple data bytes. the serial port internal byte address generator increments for each byte of the multibyte communication cycle. the ad9778 serial port controller data address will decrement from the data address written toward 0x00 for multibyte i/o operations if the msb first mode is active. the serial port controller address will increment from the data address written toward 0x1f for multibyte i/o operations if the lsb first mode is active. notes on serial port operation the ad9778 serial port configuration is controlled by reg00, bits 6 and 7 . it is important to note that the configuration changes immediately upon writing to the last bit of the register. for multibyte transfers, writing to this register may occur during the middle of communication cycle. care must be taken to compensate for this new configuration for the remaining bytes of the current communication cycle. the same considerations apply to setting the software reset, reset (reg00, bit 5). all registers are set to their default values except reg00 and reg04 which remain unchanged. use of only single byte transfers when changing serial port configurations or initiating a software reset is recommended to prevent unexpected device behavior. r/w n0 n1 a0 a1 a2 a3 a4 d7 d6 n d5 n d0 0 d1 0 d2 0 d3 0 d7 d6 n d5 n d0 0 d1 0 d2 0 d3 0 instruction cycle data transfer cycle csb sclk sdio sdo 03152-0-004 figure 25. serial register interface timing msb first a0 a1 a2 a3 a4 n1 n0 r/w d0 0 d1 0 d2 0 d7 n d6 n d5 n d4 n d0 0 d1 0 d2 0 d7 n d6 n d5 n d4 n instruction cycle data transfer cycle csb sclk sdio sdo 03152-0-005 figure 26. serial register interface timing lsb first instruction bit 6 instruction bit 7 csb sclk sdio t ds t ds t dh t pwh t pwl t sclk 03152-prd-006 figure 27. timing diagram for spi register write data bit n?1 data bit n csb sclk sdio sdo 03152-prd-007 t dv figure 28. timing diagram for spi register read
ad9778 preliminary technical data rev. pra | page 14 of 34 spi register map register name address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default comm register 00h 00 sdio bidirectional lsb,msb first software reset power down mode auto power down enable pll lock indicator 00h 01h 01 filter interpolation factor <1: 0> filter interpolation mode <4:0> zero stuffing enable 00h digital control register 02h 02 data format one port mode real mode inverse sinc enable dataclk invert iq select invert q first 00h 03h 03 data delay mode <1:0> data clock delay <2:0> data window delay <2:0> 00h 04h 04 sync out delay <3:0> sync window delay <3:0> 00h sync control 05h 05 sync enable sync driver enable dac clock offset <2:0> 00h interrupt register 06h 06 data delay irq sync delay irq cross control irq data delay irq enable sync delay irq enable cross control irq enable 00h 07h 07 pll band select <4:0> pll loop cap select <2:0> cfh pll control 08h 08 pll enable pll output freq divide <1:0> pll loop freq divide <1:0> pll loop filter pole/zero <2:0> 37h misc. control register 09h 24 pll error source pll ref bypass pll gain <2:0> pll bias <2:0> 38h 0ah 09 idac gain adjustment <7:0> f9h i dac control register 0bh 10 idac sleep idac power down idac gain adjustment <9:8> 01h 0ch 11 auxiliary dac1 data <7:0> 00h aux 1 dac control register 0dh 12 auxiliary dac1 sign auxiliary dac1 current direction auxiliary dac1 sleep auxiliary dac1 data <9:8> 00h 0eh 13 qdac gain adjustment <7;0> f9h q dac control register 0fh 14 qdac sleep qdac sleep qdac gain adjustment <9:8> 01h
preliminary technical data ad9778 rev. pra | page 15 of 34 10h 15 auxiliary dac2 data <7:0> 00h aux 2 dac control register 11h 16 auxiliary dac2 sign auxiliary dac2 current direction auxiliary dac2 power down auxiliary dac2 data <9:8> 00h 12h 17 cross updel <7:0> 00h 13h 18 cross dndel <7:0> 00h 14h 19 cross clock divide <3:0> cross wiggle delay <3:0> 00h cross register 15h 20 cross run cross status cross done cross wiggle <2:0> cross step <1:0> 00h analog write 16h 23 analog write <7:0> 00h 17h 21 mirror roll off <1:0> band gap trim <2:0> 00h analog control register 18h 22 stack headroom control<7:0> cah analog status register 19h 25 analog status <7:0> --h test 1 register 1ah 26 misr enable misr iq select misr samples internal data enable test mode <2:0> 00h 1bh 27 bist<31:24> --h 1ch 28 bist<23:16> --h 1dh 29 bist<15:8> --h test 2 register 1eh 30 bist<7:0> --h table 11 : spi register map
ad9778 preliminary technical data rev. pra | page 16 of 34 register (hex) bits na me function default 7 sdio bidirectional 0: use sdio pin as input data only 1: use sdio as both input and output data 0 6 lsb/msb first 0: first bit of se rial data is msb of data byte 1: first bit of serial da ta is lsb of data byte 0 5 software reset bit must be written with a 1, then 0 to soft reset spi register map 0 4 power down mode 0: all circuitry is active 1: disable all digital and analog ci rcuitry, only spi port is active 0 3 auto power down enable 0 00 comm register 1 pll lock (read only) 0: pll is not locked 1: pll is locked 0 7:6 filter interpolation rate 00: 1x interpolation 01: 2x interpolation 10: 4x interpolation 11: 8x interpolation 00 5:2 control halfband filters 1,2,3 see table 13 for filter modes 0000 01 digital path filter control 0 zero stuffing 0: zero stuffing off 1: zero stuffing on 0 7 data format 0: signed binary 1: unsigned binary 0 6 one port mode 0: both input data ports receive data 1: data port 1 only receives data 0 5 real mode 0: enable q pa th for signal processing 1: disable q path data (clocks disabled) 0 3 inverse sinc enable 0: inverse sinc disabled 1: inverse sinc disabled 0 2 dataclk invert 0: output dataclk sa me phase as internal capture clock 1: output dataclk opposite phase as internal capture clock 0 1 iq select invert 0: tx enable (pin 39) =1, routes input data to i channel txenable (pin 39) =0, routes input data to q channel 1: txenable (pin 39) =1, routes input data to q channel txenable (pin 39) =0, routes input data to i channel 0 02 general mode control 0 q first 0: first byte of data is al ways i data at beginning of transmit 1: first byte of data is always q data at beginning of transmit 7:6 data delay mode 00: manual, no error correction 01: manual, continuous error correction 10: automatic, one pass check 11: automatic, continuous pass check 00 5:3 data clock delay data clock delay control 000 03 data clock delay 2:0 data window delay window delay control 000 7:4 sync output delay 0000 04 synchronization delay 3:0 sync window delay 0000 7 sync enable 0: lvds and synchronization rceiver logic off 1: lvds and synchronization rceiver logic on 0 6 sync driver enable 0: lvds driver off 1: lvds driver on 0 05 chip sync and data delay control 5:3 dac clock offset 0
preliminary technical data ad9778 rev. pra | page 17 of 34 7 data delay error (read only) 0 6 chip synchronization delay error (read only) 0 5 cross control error (read only) 0 3 data delay error enable 0 2 chip synchronization error enable 0 06 irq status 1 cross control error enable 0 7:3 pll band select see table 14 for values. 11001 07 pll band and divide 2:0 pll ripple cap adjust 111 7 pll enable 0: pll off, dac rate clock supplied by outside source 1: pll on, dac rate clock synthesized in ternally from data rate clock via pll clock multiplier 0 6:5 pll output divide ratio 00: divide by 1 01: divide by 2 10: divide by 4 11: divide by 8 01 4:3 pll loop feedback divide ratio 00: divide by 1 01: divide by 2 10: divide by 4 11: divide by 8 10 08 pll enable and charge pump control 2:0 pll loop filter bandwidth tuning recommended settings. see table 14 for pll band select values. 000: pll band select 00000-00111 100: pll band select 01000-01111 110: pll band select 10000-10111 111: pll band select 11000-11111 111 7 pll error bit source 0: phase error detect 1: range limit 0 6 pll reference bypass 0: use pll reference 1: use dac reference 0 5:3 vco agc gain control. see table 14 for pll band select values. 000: pll band select 00000-00111 100: pll band select 01000-01111 110: pll band select 10000-10111 111: pll band select 11000-11111 111 09 misc. control 2:0 pll bias current level/trim 000 0a idac gain 7:0 idac gain adjustment (7:0) lsb slice of 10 bit gain setting word for idac 11111001 7 idac sleep 0: idac on 1: idac off 0 6 idac power down 0: idac on 1: idac off 0 0b idac gain and control 1:0 idac gain adjustment (9:8) msb slice of 10 bit gain setting word for idac 01 0c auxiliary dac1 gain 7:0 aux dac1 gain adjustment (7:0) lsb slice of 10 bit gain setting word for aux dac1 00000000
ad9778 preliminary technical data rev. pra | page 18 of 34 7 aux dac1 sign 0: positive 1: negative 0 6 aux dac1 direction 0: source 1: sink 0 5 aux dac1 sleep 0: aux dac1 on 1: aux dac 1 off 0 0d auxiliary dac1 control and data 1:0 aux dac1 gain adjustment (9:8) msb slice of 10 bit gain setting word for aux dac1 00 0e qdac gain 7:0 qdac gain adjustment (7:0) lsb slice of 10 bit gain setting word for qdac 11111001 7 qdac sleep 0: qdac on 1: qdac off 0 6 qdac power down 0: qdac on 1: qdac off 0 0f qdac gain and control 1:0 qdac gain adjustment (9:8) msb slice of 10 bit gain setting word for qdac 01 10 auxiliary dac2 gain 7:0 aux dac2 gain adjustment (7:0) lsb slice of 10 bit gain setting word for aux dac2 00000000 7 aux dac2 sign 0: positive 1: negative 0 6 aux dac2 direction 0: source 1: sink 0 5 aux dac2 sleep 0: aux dac1 on 1: aux dac 1 off 0 11 auxiliary dac2 control and data 1:0 aux dac2 gain adjustment (9:8) msb slice of 10 bit gain setting word for aux dac2 00 12 cross point upper delay 7:0 updelay value above zero for upper cross delay (bits 7,6, unused) 00000000 13 cross point upper delay 7:0 dndelay value below zero for lower cross delay (bits 7,6, unused) 00000000 7:3 cross control clock delay divide rate of cntclk by 2^(3:0), cntclk = 1/16 dac clock rate 00000 14 wiggle delay for cross point control 2:0 wiggle delay time step in 2^ (wiggle delay) cntclk cycles 000 7 cross run 0: disables cross control loop 1: enables cross control loop 0 6 cross status (read only) 0: control loop is lowering cross point 1: control loop is raising cross point 0 5 cross done (read only) 0: control loop is chnaging cross point value 1: control loop is holding cross point value 0 4:2 cross wiggle (2:0) number of iterations allowed in control loop 000 15 cross point control 1:0 cross step (1:0) value to change cr oss point value per iteration (wiggle) 00 16 analog write 7:0 analog write provides extra writeable control registers for analog circuit 00000000 7:6 mirror roll off frequency 00 17 mirror roll off and band gap trim 2:0 band gap trim temperature characteristic 000 output stack headroom control overdrive (current density) trim (temperature packing) 18 output stack headroom control reference offset from vdd3v (vcas centering) 19 analog status 7:0 analog status provides extr a status register for analog circuitry (unused, read only)
preliminary technical data ad9778 rev. pra | page 19 of 34 7 misr enable 0: misr disabled 1: misr enabled 0 6 misr iq select 0: read back i path signature 1: read back q path signature 0 5 misr samples 0: misr uses short sample period 1: misr uses long sample period 0 3 internal data enable 0: internal data generator off 1: internal data generator on 0 1a misr control 2:0 test mode 000: normal data port operation 001-111: to be defined test modes 000 1b misr signature register 1 7:0 misr signature (31:24) slice of 32 bit misr signature 1c misr signature register 2 7:0 misr signature (23:16) slice of 32 bit misr signature 1d misr signature register 3 7:0 misr signature (15:8) slice of 32 bit misr signature 1e misr signature register 4 7:0 misr signature (7:0) slice of 32 bit misr signature table 12: spi registerdescription
ad9778 preliminary technical data rev. pra | page 20 of 34 f_low center f_high interp. factor <7:6> filter mode <5:2> filter1 mode (mode_f1) filter2 mode (mode_f2) filter3 mode (mode_f3) modulation nyquist zone passband (freq. normalized to f dac ) 8 00h 0 0 0 dc_odd 1 -0.05 0 0.05 8 01h 1 1 0 dc_even 2 0.0125 0.0625 0.1125 8 02h 2 2 1 f/8_odd 3 0.075 0.125 0.175 8 03h 3 3 2 f/8_even 4 0.1375 0.1875 0.2375 in 8x interpolation, bw=0.0375- (0.1* f dac ) worst case: f/32 8 04h 0 4 2 2f/8_odd 5 0.2 0.25 0.3 8 05h 1 5 2 2f/8_even 6 0.2625 0.3125 0.3625 8 06h 2 6 3 3f/8_odd 7 0.325 0.375 0.425 8 07h 3 7 4 3f/8_even 8 0.3875 0.4375 0.4875 8 08h 0 0 4 -4f/8_even -8 0.45 0.5 0.55 8 09h 1 1 4 -4f/8_odd -7 0.5125 0.5625 0.6125 8 0ah 2 2 5 -3f/8_even -6 0.575 0.625 0.675 8 0bh 3 3 6 -3f/8_odd -5 0.6375 0.6875 0.7375 8 0ch 0 4 6 -2f/8_even -4 0.7 0.75 0.8 8 0dh 1 5 6 -2f/8_odd -3 0.7625 0.8125 0.8625 8 0eh 2 6 7 -f/8_even -2 0.825 0.875 0.925 8 0fh 3 7 0 -f/8_odd -1 0.8875 0.9375 0.9875 4 00h 0 0 off dc_odd 1 -0.1 0 0.1 4 01h 1 1 off dc_even 2 0.025 0.125 0.225 4 02h 2 2 off f/4_ odd 3 0.15 0.25 0.35 4 03h 3 3 off f/4_even 4 0.275 0.375 0.475 in 8x interpolation, bw=0.075-(0.2* f dac ) worst case: f/16 4 04h 0 4 off -f/2_even -4 0.4 0.5 0.6 4 05h 1 5 off -f/2_odd -3 0.525 0.625 0.725 4 06h 2 6 off -f/4_even -2 0.65 0.75 0.85 4 07h 3 7 off -f/4_odd -1 0.775 0.875 0.975 2 00h 0 off off dc_odd 1 -0.2 0 0.2 2 01h 1 off off dc_even 2 0.05 0.25 0.45 2 02h 2 off off -f/2_even -1 0.3 0.5 0.7 2 03h 3 off off -f/2_odd -2 0.55 0.75 0.95 in 2x interpolation bw=0.15-0.4 f dac worst case: f/8 table 13: interpolation filter modes, see reg 01, bits 5 :2
preliminary technical data ad9778 rev. pra | page 21 of 34 pll frequency band select pll band select value frequency in mhz 11111 (31) 804 C 850 11110 (30) 827 C 875 11101 (29) 850 C 899 11100 (28) 875 C 925 11011 (27) 899 C 951 11010 (26) 925 C 977 11001 (25) 951 C 1005 11000 (24) 977 C 1032 10111 (23) 1004 C 1061 10110 (22) 1032 C 1089 10101 (21) 1060 C 1119 10100 (20) 1089 C 1149 10011 (19) 1118 C 1179 10010 (18) 1148 C 1210 10001 (17) 1176 C 1239 10000 (16) 1206 C 1270 01111 (15) 1237 C 1302 01110 (14) 1268 C 1334 01101 (13) 1299 C 1366 01100 (12) 1331 C 1399 01011 (11) 1363 C 1432 01010 (10) 1396 C 1466 01001 (9) 1425 C 1495 01000 (8) 1458 C 1529 00111 (7) 1492 C 1563 00110 (6) 1525 C 1597 00101 (5) 1560 C 1632 00100 (4) 1594 C 1667 00011 (3) 1629 C 1702 00010 (2) 1665 C 1737 00001 (1) 1700 C 1773 00000 (0) 1735 C 1810 table 14. vco frequency range vs. pll band select value
ad9778 preliminary technical data rev. pra | page 22 of 34 internal reference/full scale current generation full scale current on the ad9778 idac and qdac can be set from 10 to 30ma. initially, the 1.2v bandgap reference is used to set up a current in an external resistor connected to i120 (pin 75). a simplified block diagram of the ad9778 reference circuitry is given below in figure 29 . the recommended value for the external resistor is 10k ? , which sets up an i reference in the resistor of 120 a. internal current mirrors provide a current gain scaling, where idac or qdac gain is a 10 bit word in the spi port register (registers 0a, 0b, 0e, and 0f). the default value for the dac gain registers gives an i fs of 20ma. 1.2v bandgap 10k ? 0.1 f current scaling dac full scale reference current idac qdac ad9778 idac gain qdac gain i120 vref figure 29 . reference circuitry where i fs is equal to; 32 gain dac 1024 6 12 27 r 1.2v ? ? ? ? ? ? ? ? ? ? ? ? ? ? + 0 5 10 15 20 25 30 35 0 200 400 600 800 1000 dac gain code i fs (ma) figure 30. i fs vs. dac gain code auxiliary dacs two auxiliary dacs are provided on the ad9778. the full scale output current on these dacs is derived from the 1.2v bandgap reference and external resistor. the gain scale from the reference amplifier to the dac reference current for each aux dac is 16.67. with the aux dac gain set to full scale (10 bit values, spi reg 0c, 0d, 10, 11), this gives a full scale current of 2ma for aux dac1 and for aux dac2. through these same spi port registers, the aux dacs can be turned off, their signs can be inverted (scale is reversed, 0-1024 gives i fs to 0), and they can be programmed for sourcing or sinking current. when sourcing current, the output compliance voltage is 0-1.5v, and when sinking current the output compliance voltage is 0.8-1.5v. the aux dacs can be used for lo cancellation when the dac output is followed by a quadrature. a typical dac to quadrature modulator interface is given in figure 31. often, the input common mode voltage for the modulator is much higher than the output compliance range of the dac, so that ac coupling is necessary. the input referred offset voltage of thee quadrature modulator can result in lo feed through on the modulator output, degrading system, performance. if the configuration of figure 29 is used, the aux dacs can be used to compensate for the input dc offset of the quad mod, thus reducing lo feedthrough. iout1_p idac qdac iout2_n iout2_p iout1_n aux1_p aux dac1 aux2_n aux2_p aux1_n aux dac2 quad mod i inputs quad mod q inputs figure 31. typical use of auxiliary dacs power down and sleep modes the ad9778 has a variety of power down modes, so that the digital engine, main txdacs, or auxiliary dacs can be powered down individually, or all at once. via the spi port, the main txdacs can be placed in sleep or powered down modes. in sleep mode, the txdac output is turned off, thus reducing power dissipation. the reference remains powered on though, so that recovery from sleep mode is very fast. when the txdac is placed in power down mode, the txdac and 1.2v bandgap reference are turned off. this mode offers more substantial power savings than in sleep mode, but the time to turn on is much longer. the auxiliary dacs also have the capability to be programmed via the spi port into sleep mode.
preliminary technical data ad9778 rev. pra | page 23 of 34 the power down bit (register 00h, bit 4) controls the power down function for the digital section of the ad9778. the power down function in bit 4 works in conjunction with txenable (pin 39) according to the following; txenable = 0:pwdwn= 0: flush data path with zeroes 1: digital engine in power down state, dacs and reference are not affected. 1: normal operation internal pll clock multiplier / clock distribution the internal clock structure on the ad9778 allows the user to drive the differential clock inputs with a clock at 1x or an integer multiple of the input data rate, or at the dac output sample rate. a pll internal to the ad9778 provides input clock multiplication and provides all of the internal clocks required for the interpolation filters and data synchronization. the internal clock architecture is shown in figure 32. the reference clock is the differential clock at pins 5 and 6. this clock input can be run differentially, or singled ended by driving pin 5 with a clock signal, and biasing pin 6 to the mid swing point of the signal at pin 5. there are various configurations in which this clock architecture can be run; 1. pll enabled (reg 08h, bit 7=1) C the pll enable switch in figure 32 is connected to the junction of the dividers n1 and n2. divider n3 determines the interpolation rate of the dac, and the ratio n2/n3 determines the ratio of reference clock/input data rate. the vco runs optimally over the range 804mhz to 1800mhz, so that n1 is used to keep the speed of the vco in this range, even though the dac sample rate may be lower. the loop filter components are entirely internal and no external compensation is necessary. 2. pll disabled (reg 08h, bit 7=0) C the pll enable switch in figure 32 is connected to the reference clock input. the differential reference clock input will be the dac output sample rate and n3 will determine the interpolation rate. figure 32. internal clock architecture of ad9778 timing information figure 33 through figure 35 show some of the various timing possibilities when the pll is enabled. the combination of the settings of n2 and n3 means that the reference clock frequency may be a multiple of the actual input data rate. figure 33 through figure 35 show, respectively, what the timing looks like when n2/n3 = 1, 2, and 4. figure 36 shows the timing specifications for the ad9778 when the pll is disabled. the reference clock is at the dac output sample rate. in the example shown in figure 36, if the pll is disabled, the interpolation is 4x.. the set up and hold time for the input data are with respect to the rising edge of the reference clock which occurs just before the rising edge of the dataclk out. note that if reg 02h, bit2 is set, dataclk out is inverted so the latching reference clock edge will occur just before the dataclk out falling edge. th ts td reference clock dataclk out input data figure 33. timing specifications for ad9778, pll enabled, reference clock = 1x input sample rate
ad9778 preliminary technical data rev. pra | page 24 of 34 th ts td reference clock dataclk out input data figure 34. timing specifications for ad9778, pll enabled, reference clock = 2x input sample rate th ts td reference clock dataclk out input data figure 35. timing specifications for ad9778, pll enabled, reference clock = 4x input sample rate th ts td ts=-2.3ns typ th=3.7ns typ td=5.5ns typ reference clock dataclk out input data figure 36. timing specifications for ad9778, pll disabled, 4x interpolation using data delay to meet timing requirements in order to meet strict timing requirements at input data rates of up to 250msps, the ad9778 has a fine timing feature. fine timing adjustments can be made by programming values into the data clock delay register (reg 03h, 5:3). by changing the values in this register, delay can be added to the default delay between the dacclk in the dataclk out. the effect of this is shown in figure 37 and figure 38. figure 37. delay from dacclk to dataclk out with clk data delay = 000 figure 38. . delay from dacclk to dataclk out with clk data delay = 111 the difference between the default delay of figure 37 and the maximum delay shown in figure 38 is the range programmable via the data clk delay register. the resulting delays when programming data clk delay between 000 and 111 are a linear extrapolation between these two figures. (typically 300ps- 400ps per increment to data clk delay).
preliminary technical data ad9778 rev. pra | page 25 of 34 interpolation filter architecture the ad9778 can provide up to 8 interpolation or disable the interpolation filters entirely. the coefficients of the low pass filters and the inverse sinc filter are given in table 5 , table 6 , table 7 , and table 8 . spectral plots for the filter responses are given in figure 3, figure 4, and figure 5. with the interpolation filter and modulator combined, the incoming signal can be placed anywhere within the nyquist region of the dac output sample rate. where the input signal is complex, this architecture allows modulation of the input signal to positive or negative nyquist regions (refer to table 13). the nyquist regions up to 4 the input data rate can be seen in figure 39. dc 1 4 3 2 -2 -3 -4 -1 1234 -1 -2 5 7 8 6 -3 -4 -5 -6 -7 -8 figure 39. nyquist zones figure 3, figure 4 and figure 5 show the low pass response of the digital filters with no modulation used. by turning on the modulation feature, the response of the digital filters can be tuned to any nyquist zone within the dac bandwidth. as an example, figure 40 to figure 46 show the odd mode filter responses (refer to table 13 for odd/even mode filter responses). -4 -3 -2 -1 0 1 2 3 4 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 figure 40. interpolation/modulation combination of -4f dac /8 filter in odd mode -4 -3 -2 -1 0 1 2 3 4 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 figure 41. interpolation/modulation combination of -3f dac /8 filter in odd mode -4 -3 -2 -1 0 1 2 3 4 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 figure 42. interpolation/modulation combination of -2f dac /8 filter in odd mode -4 -3 -2 -1 0 1 2 3 4 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 figure 43. interpolation/modulation combination of -1f dac /8 filter in odd mode
ad9778 preliminary technical data rev. pra | page 26 of 34 -4 -3 -2 -1 0 1 2 3 4 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 figure 44. interpolation/modulation combination of f dac /8 filter in odd mode -4 -3 -2 -1 0 1 2 3 4 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 figure 45. interpolation/modulation combination of 2f dac /8 filter in odd mode -4 -3 -2 -1 0 1 2 3 4 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 figure 46. interpolation/modulation combination of 3f dac /8 filter in odd mode even mode filter responses allow the passband to be centered around 0.5, 1.5, 2.5 and 3.5 f data . switching from and odd mode response to an even mode filter response does not modulate the signal. instead, the pass band is simply shifted. as an example, picture the response of figure 46, and assume the signal in band is a complex signal over the bandwidth 3.2 to 3.3 f data . if the even mode filter response is then selected, the pass band will now be centered at 3.5 f data . however, the signal will still remain at the same place in the spectrum. the even/odd mode capability allows the passband to be placed anywhere in the dac nyquist bandwidth. the ad9778 is a dual dac with an internal complex modulator built into the interpolating filter response. the modulator can be set to a real or a complex mode by programming register 02h, bit 5. in the default mode, bit 5 is set to zero and the modulation is complex. the ad9778 then expects the real and the imaginary components of a complex signal at digital input ports one and two (i and q respectively). the dac outputs will then represent the real and imaginary components of the input signal, modulated by the complex carrier f dac /2, f dac /4 or f dac /8. with bit 5 set to one, the modulation is real. the q channel is shut off and its value at the modulator inputs replaced with zero. the output spectrum at either the idac or the qdac will then represent the signal at digital input port one, real modulated by the internal digital carrier (f dac /2, f dac /4 or f dac /8).
preliminary technical data ad9778 rev. pra | page 27 of 34 evaluation board schematics figure 47. ad9778 eval board, rev b , power supply decoupling and spi interface
ad9778 preliminary technical data rev. pra | page 28 of 34 figure 48. ad9778 eval board, rev b , circuitry local to ad9778
preliminary technical data ad9778 rev. pra | page 29 of 34 figure 49. ad9778 eval board, revb , ad8349 quadrature modulator
ad9778 preliminary technical data rev. pra | page 30 of 34 figure 50. ad9778 eval board, revb , dac clock interface
preliminary technical data ad9778 rev. pra | page 31 of 34 figure 51. ad9778 eval board, revb , input port 1, digital input buffers
ad9778 preliminary technical data rev. pra | page 32 of 34 figure 52. ad9778 eval board, revb , input port 2, digital input buffers
preliminary technical data ad9778 rev. pra | page 33 of 34 outline dimensions
preliminary technical data ad9778 rev. pra | page 34 of 34 esd caution ordering guide table 15: ordering guide esd (electrostatic discharge) sensitive device. electrosta tic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although this product features proprietary esd protection circuitry, permanent damage may occur on de vices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to av oid performance degradation or loss of functionality. model temperature range description ad9778bsv -40 c to +85 c (ambient) 100-lead tqfp, exposed paddle ad9778/pcb 25c (ambient) evaluation board ? 2005 analog devices, inc. all ri ghts reserved. trademarks and registered trademarks are the prop erty of their respective owners. pr05362C0C1/05(pra)

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